1. Field of the Invention
The present invention relates to a timer device, and more particularly, to a timer device having a timer counter.
2. The Related Art
FIG. 7 is a block diagram showing one example of a conventional timer device. According to the conventional timer device, a timer counter (TC) 102 is counted up by a count clock signal 101. A comparison register (CR) 103 is connected to a bus(104) and is used for setting a coincidence signal time. A coincidence detecting circuit 105 compares the value of the timer counter (TC) 102 with that of the comparison register (CR) 103 to produce a coincidence signal 106 when both values agree with each other. A clock latch 108 (D flip flop) outputs the value of an output value setting bit (OD) 107 to an output terminal 109 for every output of the coincidence signal 106. Further, data reading and data writing with respect to the comparison register (CR) 103 and the output value setting bit (OD) 107 are carried out through the bus 104.
Now, the operation timing of a CPU in a system for carrying out key matrix control and buzzer control shown in FIG. 11 is explained by referring to the conventional timer device and software flowcharts shown in FIG. 8. In FIG. 11, a timer device 401 is connected through a bus 404 (equivalent to the bus 104 in FIG. 7) to a random access memory (RAM) 402 and a central processing unit (CPU) 403, and is also connected to a buzzer 405. A key 406 is also connected to the bus 404.
In the system described above, the CPU 403 provides a key counter (key) and a buzzer counter (buz) to the RAM 402. In other words, in accordance with a main (MAIN) program shown in FIG. 8A, the initial value key.sub.-- i of key interruption interval time and the initial value buz.sub.-- i of terminal reverse interval time are assigned in the key counter (key) and the buzzer counter (buz) (Steps 201, 202).
Then, the value of the key counter (key) is compared with that of the buzzer counter (buz) (Step 203). When the value of the key counter (key) is lower than that of the buzzer counter (buz), the value of the key counter (key) is assigned through the bus 104 in the comparison register (CR) 103 shown in FIG. 7 in the timer device 401 (Step 204). When the value of the buzzer counter (buz) is lower than that of the key counter (key), the value of the buzzer counter (buz) is assigned through the bus 104 in the comparison register (CR) 103 (Step 205). Finally, the CPU 403 enables the interruption of the timer device 401 (Step 206) to start the timer device 401 (Step 207)
In an interruption routine shown in FIG. 8B, comparison is made to see whether or not the value of the key counter (key) shown is below that of the timer counter (TC) 102 (Step 211). If the value of the key counter (key) is below that of the timer counter (TC) 102, key interruption interval time key.sub.-- i is added to the value of the key counter (key) to renew the value of the key counter (key) (Step 212).
Now, comparison is made to see whether or not the value of the buzzer counter (buz) is below the value of the timer counter (TC) 102 (Step 213). If the value of the buzzer counter (buz) is below that of the timer counter (TC) 102, terminal inverse interval time buz.sub.-- i is added to the value of the buzzer counter (buz) to renew the value of the buzzer counter (buz) (Step 214).
Now, the value of the key counter (key) is compared with that of the buzzer counter (buz) (Step 215). When the value of the buzzer counter (buz) is below that of the key counter (key), determination is then made to see whether or not the value of the output value setting bit (OD) 107 is "1" (step 216). If the reply is OD=1, the value of the output value setting bit (OD) 107 is inverted (Step 217). The value of the buzzer counter (buz) is substituted in the comparison register (CR) 103 (Step 219). On the other hand, when OD=0 is determined in Step 216, the value of the output value setting bit (OD) 107 is not inverted (Step 218), and the value of the buzzer counter (buz) is substituted for the comparison register (CR) 103 (Step 219). Meanwhile, when Step 215 determined that the value of the buzzer counter (buz) is higher than that of the key counter (key), the value of the key counter (key) is substituted in the comparison register (CR) 103 (Step 220).
FIG. 9 shows a time chart for explaining the operation of the conventional timer device described above, and shows an example of buz.sub.-- i=600 H, key.sub.-- i=1100 H (Hexidecimel). The initial value 1100 H is set to the key counter (key) (Step 201). The initial value 600 H is set to the buzzer counter (buz) (Step 202). The value (600 H) of the buzzer counter (buz) is lower than the value (1100 H) of the key counter (key). Accordingly, the value (600 H) of the buzzer counter (buzz) is substituted for the comparison register (CR) 103 (Steps 203 and 205). Then, timer interruption is enabled to start the timer (Steps 206 and 207).
When the value of the timer counter (TC) 102 equalizes to the value (600 H) of the comparison register (CR) 103, the value of the output value setting bit (OD) 107 is output to the output terminal 109. Interruption is simultaneously generated. In the interruption routine, the value (600 H) of the buzzer counter (buz) is lower than that of the timer counter (TC) 102. Thus, the value of the buzzer counter (buz) is added to yield C00 H (Step 214). Comparison of the value (C00 H) of the added value of the buzzer counter (buz) with the value (1100 H) of the key counter (key) discloses that the value (C00 H) of the added buzzer counter (buz) is lower than the value (1100 H) of the key counter (key). Thus, the output value setting bit (OD) 107 is inverted (Steps 216, 217 or 218) to assign the value (C00 H) of the buzzer counter (buz) in the comparison register (CR) 103 (Step 219), terminating the interruption processing.
Now, when the value of the timer counter (TC) 102 equalizes to the value (C00 H) of the comparison register (CR) 103, the value of the output value setting bit (OD) 107 is output to the output terminal 109 (output of the output terminal 109 is inverted).
In the interruption routine, the value (C00 H) of the timer counter (TC) 102 is equal to the value (C00 H) of the buzzer counter (buz). Thus, buz.sub.-- i=600 H is added to the value of the buzzer counter (buz). The value of the buzzer counter (buz) yields 1200 H (Steps 213, 214). Then, comparison of the value (1100 H) of the key counter (key) with the added value (1200 H) of the buzzer counter (buz) (Step 215) discloses that the value of the key counter (key) is lower than that of the buzzer counter (buz). Thus, the value (1100 H) of the key counter (key) is substituted in the comparison register (CR) 103, terminating the interruption processing (output value setting bit (OD) 107 is not allowed to inverse).
Now, when the value of the timer counter (TC) 102 equalizes to the value (1100 H) of the comparison register (CR) 103, the value of the output value setting bit (OD) 107 is output to the output terminal 109(output of the output terminal 109 is not inverted). Simultaneously, the interruption routine is activated.
In the interruption routine, the value (1100 H) of the timer counter (TC) 102 is compared with the value (1100 H) of the key counter (key) (Step 211). Since both the values are equal, key.sub.-- i=1100 H is added to the value of the key counter (key). The value of the key counter (key) yields 2200 H (Steps 212). Then, key fetching processing is carried out. Comparison of the value (1200 H) of the buzzer counter (buz) with the value (2200 H) of the key counter (key) (Step 215) discloses that the value of the buzzer counter (buz) is lower than that of the key counter (key). Thus, the output value setting bit (OD) 107 is inverted (Steps 216, 217). The value (1200 H) of the buzzer counter (buz) is substituted for the comparison register (CR) 103 (Step 219), terminating the interruption processing.
In this way, executing this software inverses the output of the output terminal 109 for every 600 H of the timer counter (TC) 102 to sound a buzzer 405 in FIG. 11, carrying out data fetching processing for a key 406 for every 1100 H of the timer counter (TC) 102.
Now, timing for carrying out buzzer control only by using the conventional timer device is explained by referring to software flow charts in FIG. 10. The main program in FIG. 10A substitute buz.sub.-- i for the comparison register (CR) 103 (Step 301) to enable the interruption of the timer device (Step 303), starting the timer (Step 304). In the interruption routine shown in FIG. 10B and activated in the CPU for every output of the coincidence signal from the timer device, the output value setting bit (OD) 107 is inverted (Steps 321, 322 or 323). Buz.sub.-- i is then added to the comparison register (CR) 103. The added buz.sub.-- i is set as a new value of the comparison register (CR) through the bus 404 (104) (Step 324).
The conventional timer device described above, however, requires for setting (for example, step 216 to 218 of FIG. 8B) of the output value setting bit (OD) 107 by the interruption process when the timer device is used for the inverse output of the output terminal 109. This prolongs software processing duration and result in problems access timing becomes tight.